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A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems
Network-on-Chip (NoC) paradigm is rapidly evolving into an efficient interconnection network to handle the strict communication requirements between the increasing number of cores on a single chip. Diminishing transistor size is making the NoC increasingly vulnerable to both hard faults and soft errors. This paper concentrates on soft errors in NoCs. A soft error in an NoC router results in sig…
- Edisi
- VOL. 14, NO. 2, JULY-DECEMBER 2015
- ISBN/ISSN
- Digital Object Ident
- Deskripsi Fisik
- IEEE COMPUTER ARCHITECTURE LETTERS, VOL. 14, NO. 2, JULY-DECEMBER 2015
- Judul Seri
- COMPUTER ARCHITECTURE
- No. Panggil
- -
A Methodology for Cognitive NoC Design
The number of cores in a multicore chip design has been increasing in the past two decades. The rate of increase will continue for the foreseeable future. With a large number of cores, the on-chip communication has become a very important design consideration. The increasing number of cores will push the communication complexity level to a point where managing such highly complex systems requir…
- Edisi
- -
- ISBN/ISSN
- DOI 10.1109/LCA.2015
- Deskripsi Fisik
- IEEE Computer Architecture Letters
- Judul Seri
- Computer Architecture
- No. Panggil
- -
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