Ditapis dengan
ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.1…
Abstract One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra “ESD implantation” mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18- m salicided CMOS process is investigated by experimental testchips. The second breakdown current ( 2) o…
- Edisi
- VOL. 18, NO. 2, MAY 2005
- ISBN/ISSN
- 0894-6507
- Deskripsi Fisik
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 2, MAY 2005
- Judul Seri
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 2, MAY 2005
- No. Panggil
- -
Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by L…
This paper presented a practical industry case of electrical overstress (EOS) failure induced by the latchup test in high-voltage integrated circuits (ICs). By using proper layout modification and additional circuit, the unexpected EOS failure, which is caused by negative-current-triggered latchup test, can be successfully solved. The new design with proposed solutions has been verified in the …
- Edisi
- VOL. 14, NO. 1, MARCH 2014
- ISBN/ISSN
- DOI: 10.1109/TDMR.20
- Deskripsi Fisik
- IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014
- Judul Seri
- IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
- No. Panggil
- -
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