Analysis of Temperature Distribution in Stacked IC With On-Chip Sensing Devic…

Abstract Temperature distributions in 3-D integrated circuits (ICs) are analyzed with a test structure, which has a top-tier chip attached on a bottom dummy chip with adhesive layer. The devices with four kinds of top-tier chip thickness tSi of 50–410 μm were fabricated by a standard 0.18 μm CMOS process. The test structure consists of 24 sensor blocks, each of which has sensor p-n diodes…