e-journal

System-Level ESD Protection Design Using On-Wafer Characterization and Transient Simulations

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A methodology for the design of circuits robust to system-level electrostatic discharge (ESD) stress is presented and verified with two case studies. The combination of on-wafer characterization and transient simulations enables the ESD designer to study the behavior of the component-level ESD protection design during system-level ESD stress with and without adding off-chip protection devices. The design of a system-level ESD protection solution can be verified long before IC packaging and even before the final system is built.

Index Terms: Electrostatic discharge (ESD), integrated circuit (IC) reliability, reliability, system analysis and design.

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Ketersediaan

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Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY

No. Panggil

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Penerbit

New York : IEEE., 2014

Deskripsi Fisik

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014

Bahasa

English

ISBN/ISSN

DOI: 10.1109/TDMR.20

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 14, NO. 1, MARCH 2014

Subjek

ELEKTRONIK

Info Detail Spesifik

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Pernyataan Tanggungjawab

agus

Versi lain/terkait

Lampiran Berkas

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