Gaya APA

Ker, M. et al (2005). ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.18-um Salicided CMOS Technology (VOL. 18, NO. 2, MAY 2005). : IEEE.

Gaya MLA

Ker, Ming-Dou. et al. "ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.18-um Salicided CMOS Technology". VOL. 18, NO. 2, MAY 2005 : IEEE, 2005. e-journal.