e-journal

Full-Wafer Voltage Contrast Inspection for Detection of BEOL Defects

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Abstract
This paper details an application where E-beam inspection (EBI) can be used for 100% full wafer inspection, generally considered a mythical target for EBI. For process layers where the line-widths and defects of interest are large, very large pixel size and high scan frequency can be used, thereby making full wafer inspection feasible. The metal layers in the back-endof-line fit this bill when scanned in voltage contrast (VC) mode. Shorts or opens at any previous layer connected to the surface
nodes can cause a VC signal, therefore the electrical health of each wafer is assessed for multiple layers simultaneously across the full wafer. The advantage of this scan is that failure sites
can be identified and somewhat localized well before wafer final test. This application is more appropriate for semi-mature technologies where there are few defects per wafer, and therefore
a full wafer scan is needed to catch a reasonable number of defects. The challenge with this type inspection is in identification of the root cause. A number of studies to map VC defect strength to types of physical defects are described. These studies demonstrated that this technique successfully finds yield limiting defects, but not all yield limiting defects will be detected. A plan for how to use the VC inspection to find root cause is presented.

Index Terms—EBI, electron beam inspection, full-wafer inspection, shorts, opens, defects, voltage contrast

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Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015

No. Panggil

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Penerbit

: IEEE., 2015

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015

Bahasa

English

ISBN/ISSN

0894-6507

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 28, NO. 4, NOVEMBER 2015

Subjek

SEMIKONDUKTOR

Info Detail Spesifik

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Pernyataan Tanggungjawab

ETY

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