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Impact of Gate Induced Drain Leakage on Overall Leakage of Submicrometer CMOS VLSI Circuits

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Abstract
In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal–oxide–semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits.We present the experimental and simulation data of GIDL current as a function of 0.35- m CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield.

Index Terms—Band-to-band tunneling, CMOS ICs reliability, gate-induced leakage current, standard logic cells layout

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Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 15, NO. 1, FEBRUARY 2002

No. Panggil

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Penerbit

: IEEE., 2002

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 15, NO. 1, FEBRUARY 2002

Bahasa

English

ISBN/ISSN

0894-6507

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 15, NO. 1, FEBRUARY 2002

Subjek

SEMIKONDUKTOR

Info Detail Spesifik

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Pernyataan Tanggungjawab

ETY

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