e-journal

Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor

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Abstract
In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being matched with a verification wafer. The proposed method makes the ability to apply a different voltage trimming
condition for each dies internal voltage circuit depending on their characteristics, thereby improving the characteristics of the individual dies and reducing the fail bit count (FBC) further. The
experimental results on the real-application case show that our proposed method reduces the FBC by 1%–5%, which contributes yield enhancement and quality improvement of DRAM memory by raising the efficiency of the redundancy cell repair in the repair process.

Index Terms—Semiconductor, dynamic random access memory (DRAM), wafer memory test, electric die sort (EDS), memory repair, voltage trimming circuit.

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Ketersediaan

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Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 2, MAY 2015

No. Panggil

-

Penerbit

: IEEE., 2015

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 2, MAY 2015

Bahasa

English

ISBN/ISSN

0894-6507

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 28, NO. 2, MAY 2015

Subjek

SEMIKONDUKTOR
DRAM
MEMORY

Info Detail Spesifik

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Pernyataan Tanggungjawab

ETY

Versi lain/terkait

Lampiran Berkas

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