Gaya APA

[et.al.], D, Z. (2015). Process Development and Optimization for 3 μm High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level (VOL. 28, NO. 4, NOVEMBER 2015). : IEEE.

Gaya MLA

[et.al.], Dingyou, Zhang. "Process Development and Optimization for 3 μm High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level". VOL. 28, NO. 4, NOVEMBER 2015 : IEEE, 2015. e-journal.