Process Development and Optimization for 3 μm High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

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Process Development and Optimization for 3 μm High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

Dingyou Zhang [et.al.] - Nama Orang;

Abstract—This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 μm top entrant critical dimension and 50 μm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 μm TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.

Index Terms—TSV, high aspect ratio, etch, electroplating, KOZ, 3D.

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Judul Seri: IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015
No. Panggil: -
Penerbit: : IEEE., 2015
Deskripsi Fisik: IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015
Bahasa: English
ISBN/ISSN: 0894-6507
Klasifikasi: -
Tipe Isi: -
Tipe Media: -
Tipe Pembawa: -
Edisi: VOL. 28, NO. 4, NOVEMBER 2015
Subjek: SEMIKONDUKTOR
Info Detail Spesifik: -
Pernyataan Tanggungjawab: ETY

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Process Development and Optimization for 3 μm High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

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