e-journal

Using Wafer Map Features to Better Predict Die-Level Failures in Final Test

---

Abstract—In semiconductor manufacturing, wafer fabrication is followed by chip assembly where individual dies are assembled as a packaged chip. In between, dies are tested in terms of their electrical properties and those which fail to pass the “wafer test” are filtered out. However, some faulty dies pass the test and cause a packaged chip to fail in the final test. The inaccuracy of the wafer test leads to waste in manufacturing time and cost. In this paper, we propose to predict the result of the final test at the die-level before assembly using wafer test items and four derivations concerning wafer map features: 1) distance of the die from the wafer center; 2) previous final
yield at the die position; 3) wafer test fail rate for the adjacent dies; and 4) abnormalities of the wafer map pattern. We build prediction models with these variables using a random forest algorithm. Preliminary experimental results on actual data show that the use of these derived variables improves the prediction performance with a statistical significance, thus merits further investigation.

Index Terms—Die-level failure, wafer map feature, yield prediction, final test, wafer test, random forest.

---

Ketersediaan

Tidak ada salinan data

Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

No. Panggil

-

Penerbit

: IEEE., 2015

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

Bahasa

English

ISBN/ISSN

0894-6507

Klasifikasi

-

Tipe Isi

-

Tipe Media

-

Tipe Pembawa

-

Edisi

VOL. 28, NO. 3, AUGUST 2015

Subjek

SEMIKONDUKTOR

Info Detail Spesifik

-

Pernyataan Tanggungjawab

ETY

Versi lain/terkait

Lampiran Berkas

Komentar

---

Anda harus masuk sebelum memberikan komentar