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A 0.4-mW, 4.7-ps Resolution Single-Loop  TDC Using a Half-Delay Time Integrator

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Abstract—A compact, low-power, single-loop third-order delta–sigma () time-to-digital converter (TDC) for time-mode signal processing is presented in this brief. In general, a high-resolution
 TDC requires a cascadable time integrator to increase the order of the loop filter. However, implementing the time integrator has been very challenging owing to the difficulty in storing time information. In this brief, we present a low-power half-delay time integrator, which is simply
composed of two AND gates, a charge pump, and a comparator. The proposed time integrator can be easily cascaded (serially connected) to implement a loop filter with high-order noise shaping. The prototype
TDC fabricated in 0.11-μm CMOS process occupies an active area of 0.11 mm2, consuming 0.4 mW from a 1.2 V supply. It achieves the dynamic range of 81 dB over a signal bandwidth of 50 kHz, and the resolution of 4.7 ps over a measurable range of 39.06 ns, which is half the clock period.

Index Terms—Delta–sigma () modulator, high resolution, low power, time-to-digital converter (TDC).

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Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 3, MARCH 2016

No. Panggil

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Penerbit

: IEEE., 2016

Deskripsi Fisik

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Bahasa

English

ISBN/ISSN

1063-8210

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 24, NO. 3, MARCH 2016

Subjek

VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Info Detail Spesifik

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Pernyataan Tanggungjawab

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Versi lain/terkait

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