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Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation

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To meet the electrical performance requirements, copper traces with ultralow-k (ULK) interlayer dielectric (ILD) materials are used in today’s semiconductor devices. The dielectric constant (k) of these materials is often reduced through the introduction of pores or inclusions, and thus, the ULK ILD materials have low fracture strength. During flip-chip assembly, thermally induced stresses occurring due to the differential displacement between the substrate and the die can result either in ILD cracking or in ILD delamination in the vicinity of solder bump. Such reliability problems are a cause for concern in semiconductor devices. In this paper, we study such dielectric cracking through numerical
models and experiments and present methods to reduce such dielectric cracking. This work uses a finite-element-based submodeling approach to study ILD cracking in flip-chip assemblies. The developed “global” model accounts for the die, the passivation layer, the die pad, the solder bump, the substrate pad, and various layers in the substrate, including the trace pattern effective directional modulus. The displacement boundary conditions from the global model under flip-chip assembly cooling are then applied to a “local model,” which accounts for the die with its backend-of-line (BEOL) stack details, such as the die pad, the passivation layer, the solder bump, the substrate pad, and layers in the substrate. The local model focuses on the most critical solder bump, based on global stress contours. Next, cohesive cracks are introduced at various locations in the ULK layers above the critical solder bump and are allowed to propagate under flip-chip assembly reflow thermal conditions. It can be seen that the elastic energy available for crack propagation initially increases with crack length, but then starts to decay, indicating that the ILD cracking is often confined in the vicinity of one bump. Furthermore, the results
from the models have been compared against experimental failure analysis results of 45-nm (C45) devices. It is also shown that the models can provide geometry and material guidelines to reduce ILD cracking.
Index Terms—Back end of line (BEOL) stack reliability, finite-element modeling, flip-chip devices, focused ion beam (FIB), fracture mechanics simulation, lead-free solder reflow, low-k dielectric
thin films, microelectronic packaging, porous low-k dielectric, thin film delamination, ultra low-k dielectric cracking.

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Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY

No. Panggil

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Penerbit

New York : IEEE., 2014

Deskripsi Fisik

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014

Bahasa

English

ISBN/ISSN

1530-4388

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 14, NO. 1, MARCH 2014

Subjek

TEKNIK

Info Detail Spesifik

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Pernyataan Tanggungjawab

Yuli/Agus

Versi lain/terkait

Lampiran Berkas

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