A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

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A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

Yankang Du - Nama Orang; Shuming Chen - Nama Orang; Biwei Liu - Nama Orang;

A novel constrained layout placement approach is proposed to enhance the pulse quenching effect in combinational circuits. This constrained algorithm can enlarge the number of quenching cells and shrink the distance between these cells. Simulation results illustrate that the soft error vulnerabilities are effectively reduced by adopting this novel constrained layout placement algorithm with no area penalty.
Index Terms—Constrained layout, multi-node charge collection, pulse quenching effect, quenching cells.

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Judul Seri: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
No. Panggil: -
Penerbit: New York : IEEE., 2014
Deskripsi Fisik: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014
Bahasa: English
ISBN/ISSN: 1530-4388
Klasifikasi: -
Tipe Isi: -
Tipe Media: -
Tipe Pembawa: -
Edisi: VOL. 14, NO. 1, MARCH 2014
Subjek: TEKNIK
Info Detail Spesifik: -
Pernyataan Tanggungjawab: Yuli/Agus

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FULL TEXT. A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

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