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Single-Error-Correction and Double-Adjacent-Error-Correction Code for Simultaneous Testing of Data Bit and Check Bit Arrays in Memories

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In this paper, a new single-error-correction and double-adjacent-error-correction (SEC-DAEC) code is proposed for simultaneous testing of the most general memory fault models in both data bit and check bit arrays of memories. Simultaneous testing of data bit and check bit arrays eliminates the test time and
hardware overheads required for separate check bit array tests. In order to test data bit and check bit arrays simultaneously, the proposed SEC-DAEC code generates the identical data background patterns for data bit and check bit arrays. The testable faults using the proposed SEC-DAEC code are the most general memory fault models such as single-cell faults and interword and intraword coupling faults. Simultaneous testing of data bit and check bit arrays using the proposed SEC-DAEC codes brings significant decreases of about 27.3%, 17.9%, and 11.1% in the time required for memory array tests for 16, 32, and 64 data bits per word, respectively. In addition, the number of ones in the H-matrix of the proposed SEC-DAEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator.
Index Terms—Error correction code, fault model, memory test,word-oriented memory.

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Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY

No. Panggil

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Penerbit

New York : IEEE., 2014

Deskripsi Fisik

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014

Bahasa

English

ISBN/ISSN

1530-4388

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 14, NO. 1, MARCH 2014

Subjek

TEKNIK

Info Detail Spesifik

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Pernyataan Tanggungjawab

Yuli/Agus

Versi lain/terkait

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