Gaya APA

Poluri, P., Louri, A. (2015). A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems (VOL. 14, NO. 2, JULY-DECEMBER 2015). Sweden: IEEE COMPUTER ARCHITECTURE LETTERS,.

Gaya MLA

Poluri, Pavan., Louri, Ahmed. "A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems". VOL. 14, NO. 2, JULY-DECEMBER 2015 Sweden: IEEE COMPUTER ARCHITECTURE LETTERS,, 2015. e-journal.