Accelerator Memory Reuse in the Dark Silicon Era | Elibrary Perpustakaan Universitas Riau

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Accelerator Memory Reuse in the Dark Silicon Era

Emilio G. Cota [et al..] - Nama Orang;

Accelerators integrated on-die with General-Purpose CPUs (GP-CPUs) can yield significant performance and power improvements. Their extensive use, however, is ultimately limited by their area overhead; due to their high degree of specialization, the opportunity cost of investing die real estate on accelerators can become prohibitive, especially for general-purpose architectures. In this paper we present a novel technique aimed at mitigating this opportunity cost by allowing GP-CPU cores to reuse accelerator memory as a non-uniform cache architecture (NUCA) substrate. On a system with a last level-2 cache of 128kB, our technique achieves on average a 25% performance improvement when reusing four 512 kB accelerator memory blocks to form a level-3 cache. Making these blocks reusable as NUCA slices incurs on average in a 1.89% area overhead with respect to equally-sized ad hoc cache slices.

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Judul Seri: COMPUTER ARCHITECTURE
No. Panggil: -
Penerbit: Sweden : Graduate School of Economics, Waseda University., 2014
Deskripsi Fisik: IEEE COMPUTER ARCHITECTURE LETTERS, VOL. 13, NO. 1, JANUARY-JUNE 2014
Bahasa: English
ISBN/ISSN: Digital Object Ident
Klasifikasi: -
Tipe Isi: -
Tipe Media: -
Tipe Pembawa: -
Edisi: VOL. 13, NO. 1, JANUARY-JUNE 2014
Subjek: ARSITEKTUR KOMPUTER
Info Detail Spesifik: -
Pernyataan Tanggungjawab: deliza

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FULLTEXT: Accelerator Memory Reuse in the Dark Silicon Era

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