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Architectural Reliability: Lifetime Reliability Characterization and Management of Many-Core Processors

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This paper presents a lifetime reliability characterization of many-core processors based on a full-system simulation of integrated microarchitecture, power, thermal, and reliability models. Under normal operating conditions, our model and analysis reveal that the mean-time-to-failure of cores on the die show normal distribution. From the processor-level perspective, the key insight is that reducing the variance of the distribution can improve lifetime reliability by avoiding early failures. Based on this understanding, we present two variance reduction techniques for proactive reliability management; i) proportional dynamic voltagefrequency scaling (DVFS) and ii) coordinated thread swapping. A major advantage of using variance reduction techniques is that the improvement of system lifetime reliability can be achieved without adding design margins or spare components.

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Ketersediaan

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Informasi Detail

Judul Seri

COMPUTER ARCHITECTURE

No. Panggil

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Penerbit

Sweden : IEEE Computer Architecture Letters., 2015

Deskripsi Fisik

IEEE COMPUTER ARCHITECTURE LETTERS, VOL. 14, NO. 2, JULY-DECEMBER 2015

Bahasa

English

ISBN/ISSN

Digital Object Ident

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 14, NO. 2, JULY-DECEMBER 2015

Subjek

ARSITEKTUR KOMPUTER

Info Detail Spesifik

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Pernyataan Tanggungjawab

deliza

Versi lain/terkait

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