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Architectural Support for Mitigating Row Hammering in DRAM Memories

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DRAM scaling has been the prime driver of increasing capacity of main memory systems. Unfortunately, lower technology nodes worsen the cell reliability as it increases the coupling between adjacent DRAM cells, thereby exacerbating different failure modes. This paper investigates the reliability problem due to Row Hammering, whereby frequent activations of a given row can cause data loss for its neighboring rows. As DRAM scales to lower technology nodes, the threshold for the number of row activations that causes data loss for the neighboring rows reduces, making Row Hammering a challenging problem for future DRAM chips. To overcome Row Hammering, we propose two architectural solutions: First, Counter-Based Row Activation (CRA), which uses a counter with each row to count the number of row activations. If the count exceeds the row hammering threshold, a dummy activation is sent to neighboring rows proactively to refresh the data. Second, Probabilistic Row Activation (PRA), which obviates storage overhead of tracking and simply allows the memory controller to proactively issue dummy activations to neighboring rows with a small probability for all memory access. Our evaluations show that these solutions are effective at mitigating Row hammering while causing negligible performance loss (< 1 percent).

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Informasi Detail

Judul Seri

COMPUTER ARCHITECTURE

No. Panggil

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Penerbit

Sweden : IEEE Computer Architecture Letters., 2015

Deskripsi Fisik

IEEE COMPUTER ARCHITECTURE LETTERS, VOL. 14, NO. 1, JANUARY-JUNE 2015

Bahasa

English

ISBN/ISSN

Digital Object Ident

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 14, NO. 1, JANUARY-JUNE 2015

Subjek

ARSITEKTUR KOMPUTER

Info Detail Spesifik

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Pernyataan Tanggungjawab

deliza

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