e-journal

CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults

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Faulty cells have become major problems in cost-sensitive main-memory DRAM devices. Conventional solutions to reduce device failure rates due to cells with permanent faults, such as populating spare rows and relying on errorcorrecting codes, have had limited success due to high area overheads. In this paper, we propose CIDR, a novel cache-inspired DRAM resilience architecture,
which substantially reduces the area overhead of handling bit errors from these faulty cells. A DRAM device adopting CIDR has a small cache next to its I/O pads to replace accesses to the addresses that include the faulty cells with ones that correspond to the cache data array. We minimize the energy overhead of accessing the cache tags for every read or write by adding a Bloom filter in front of the cache. The augmented cache is programmed once during the testing phase and is out of the critical path on normal accesses because both cache and DRAM arrays
are accessed in parallel, making CIDR transparent to existing processor-memory interfaces. Compared to the conventional architecture relying on spare rows, CIDR lowers the area overhead of achieving equal failure rates over a wide range of single-bit error rates, such as 23.6
lower area overhead for a bit-error rate of 105 and a device failure rate of 103.

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Informasi Detail

Judul Seri

COMPUTER ARCHITECTURE

No. Panggil

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Penerbit

Sweden : Graduate School of Economics, Waseda University., 2015

Deskripsi Fisik

IEEE COMPUTER ARCHITECTURE LETTERS, VOL. 14, NO. 1, JANUARY-JUNE 2015

Bahasa

English

ISBN/ISSN

Digital Object Ident

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 14, NO. 1, JANUARY-JUNE 2015

Subjek

ARSITEKTUR KOMPUTER

Info Detail Spesifik

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Pernyataan Tanggungjawab

deliza

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