Flattened Butterly Topology for On-Chip Networks | Elibrary Perpustakaan Universitas Riau

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Flattened Butterly Topology for On-Chip Networks

John Kim - Nama Orang; James Balfour - Nama Orang; William J. Dally - Nama Orang;

With the trend towards increasing number of cores in a multicore processors, the on-chip network that connects the cores needs to scale efciently. In this work, we propose the use of high-radix networks in on-chip networks and describe how the attened buttery topology can be mapped to on-chip networks. By using high-radix routers to reduce the diameter of the network, the attened buttery offers lower latency and energy consumption than conventional on-chip topologies. In addition, by properly using bypass channels in the attened buttery network, non-minimal routing can be employed without increasing latency or the energy consumption

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Judul Seri: COMPUTER ARCHITECTURE
No. Panggil: -
Penerbit: Sweden : IEEE Computer Architecture Letters., 2007
Deskripsi Fisik: IEEE COMPUTER ARCHITECTURE LETTERS, VOL. 6, NO. 2, JULY-DECEMBER 2007
Bahasa: English
ISBN/ISSN: -
Klasifikasi: -
Tipe Isi: -
Tipe Media: -
Tipe Pembawa: -
Edisi: VOL. 6, NO. 2, JULY-DECEMBER 2007
Subjek: ARSITEKTUR KOMPUTER
Info Detail Spesifik: -
Pernyataan Tanggungjawab: deliza

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FULLTEXT: Flattened Butterly Topology for On-Chip Networks

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