e-journal

Revisiting Using the Results of Pre-Executed Instructions in Runahead Processors

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Long-latency cache accesses cause significant performance-impacting delays for both in-order and out-of-order processor systems. To address these delays, runahead pre-execution has been shown to produce speedups by warming-up cache structures during stalls caused by long-latency memory accesses. While improving cache related performance, basic runahead approaches do not otherwise
utilize results from accurately pre-executed instructions during normal operation. This simple model of execution is potentially inefficient and performance constraining. However, a previous study showed that exploiting the results of accurately pre-executed runahead instructions for out-of-order processors provide little performance improvement over simple re-execution. This work will show that, unlike out-of-order runahead architectures, the performance improvement from runahead result use for an in-order pipeline is more significant, on average, and in some situations provides dramatic performance improvements. For a set of SPEC CPU2006 benchmarks which
experience performance improvement from basic runahead, the addition of result use to the pipeline provided an additional speedup of 1.14X (high – 1.48X) for an in-order processor model compared to only 1.05X (high – 1.16X) for an out-of-order one. When considering benchmarks with poor data cache locality, the average speedup increased to 1.21X for in-order compared to only 1.10X for out-of-order.

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Informasi Detail

Judul Seri

COMPUTER ARCHITECTURE LETTERS

No. Panggil

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Penerbit

Sweden : IEEE Computer Architecture Letters., 2014

Deskripsi Fisik

IEEE COMPUTER ARCHITECTURE LETTERS, VOL. 13, NO. 2, JULY-DECEMBER 2014

Bahasa

English

ISBN/ISSN

Digital Object Ident

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

(2014), VOL. 13, NO. 2.

Subjek

ARSITEKTUR KOMPUTER

Info Detail Spesifik

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Pernyataan Tanggungjawab

deliza

Versi lain/terkait

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