e-journal

Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core

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As thread level parallelism in applications has continued to expand, so has research in chip multi-core processors. As more and more applications become multi-threaded we expect to find a growing number of threads executing on a machine. As a consequence, the operating system will require increasingly larger amounts of CPU time to schedule these threads efficiently. Instead of
perpetuating the trend of performing more complex thread scheduling in the operating system, we propose a scheduling mechanism that can be efficiently implemented in hardware as well. Our approach of identifying multi-threaded application bottlenecks such as thread synchronization sections complements the Fairness-aware Scheduler method. It achieves an average speed up of
11.5 percent (geometric mean) compared to the state-of-the-art Fairness-aware Scheduler.

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Informasi Detail

Judul Seri

COMPUTER ARCHITECTURE LETTERS

No. Panggil

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Penerbit

Sweden : IEEE Computer Architecture Letters., 2015

Deskripsi Fisik

IEEE COMPUTER ARCHITECTURE LETTERS, VOL. 14, NO. 2, 160-163, 2015

Bahasa

English

ISBN/ISSN

Digital Object Ident

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

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Subjek

ARSITEKTUR KOMPUTER

Info Detail Spesifik

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Pernyataan Tanggungjawab

deliza

Versi lain/terkait

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