e-journal

Towards High-Performance Bufferless NoCs with SCEPTER

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In the many-core era, the network on-chip (NoC) is playing a larger role in meeting performance, area and power goals, as router buffers contribute greatly to NoC area and power usage. Proposals have advocated bufferless NoCs, however a performance wall has been reached such that high throughput performance has not been extracted. We present SCEPTER, a high-performance bufferless mesh NoC that sets up single-cycle virtual express paths dynamically across the chip, allowing deflected packets to go through non-minimal paths with no latency penalty. For a 64 node network, we demonstrate an average 62% reduction in latency and an average 1.3 higher throughput over a baseline bufferless NoC for synthetic traffic patterns; with comparable performance to a Single-cycle multihop buffered mesh network with 6 flit buffers, per input port, in each router.

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Informasi Detail

Judul Seri

Computer Architecture

No. Panggil

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Penerbit

Sweden : IEEE Computer Architecture Letters., 2015

Deskripsi Fisik

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Bahasa

English

ISBN/ISSN

DOI 10.1109/LCA.2015

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

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Subjek

ARSITEKTUR KOMPUTER

Info Detail Spesifik

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Pernyataan Tanggungjawab

deliza

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