TBM: Twin Block Management Policy to Enhance the Utilization of Plane-Level …

The internal architecture of a SSD provides channel-, chip-, die- and plane-level parallelism Levels, to concurrently perform multiple data accesses and compensate for the performance gap between a single flash chip and host interface. Although a good strategy can effectively exploit the first 3 levels, parallel I/O accesses at plane-level can be performed only for operations of the same types …