Drop Impact Reliability Analysis of 3-D Chip-on-Chip Packaging: Numerical Mod…

This paper aims at investigating the drop impact solder interconnect reliability of an advanced ultra-fine-pitch 3-D integrated circuit chip stacking packaging in accordance with JEDEC board-level test specification through finite-element (FE) simulation and experimental testing. To characterize the transient dynamic responses of the package, ANSYS/LS-DYNA incorporated with the Input-G method i…