Ditapis dengan
Using Wafer Map Features to Better Predict Die-Level Failures in Final Test
Abstract—In semiconductor manufacturing, wafer fabrication is followed by chip assembly where individual dies are assembled as a packaged chip. In between, dies are tested in terms of their electrical properties and those which fail to pass the “wafer test” are filtered out. However, some faulty dies pass the test and cause a packaged chip to fail in the final test. The inaccuracy of the …
- Edisi
- VOL. 28, NO. 3, AUGUST 2015
- ISBN/ISSN
- 0894-6507
- Deskripsi Fisik
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015
- Judul Seri
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015
- No. Panggil
- -
Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor
Abstract In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being match…
- Edisi
- VOL. 28, NO. 2, MAY 2015
- ISBN/ISSN
- 0894-6507
- Deskripsi Fisik
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 2, MAY 2015
- Judul Seri
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 2, MAY 2015
- No. Panggil
- -
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