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Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits

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This paper presented a practical industry case of electrical overstress (EOS) failure induced by the latchup test in high-voltage integrated circuits (ICs). By using proper layout modification and additional circuit, the unexpected EOS failure, which is caused by negative-current-triggered latchup test, can be successfully solved. The new design with proposed solutions has been verified in the 0.6-μm 40-V Bipolar CMOS DMOS (BCD) process to pass the test for at least 500-mA trigger current, which shows high negative-current-latch-up immunity without
overstress damage, compared with the protection of only the guard ring. Such solutions can be adopted to implement high-voltage-applicable IC product to meet the industry requirement for the mass production of IC manufactures and applications.

Index Terms—Electrical overstress (EOS), high-voltage CMOS, latchup, regulator.

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Ketersediaan

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Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY

No. Panggil

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Penerbit

New York : IEEE., 2014

Deskripsi Fisik

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014

Bahasa

English

ISBN/ISSN

DOI: 10.1109/TDMR.20

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 14, NO. 1, MARCH 2014

Subjek

ELEKTRONIK

Info Detail Spesifik

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Pernyataan Tanggungjawab

agus

Versi lain/terkait

Lampiran Berkas

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