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Fabrication, Characterization, and Simulation of a Low-cost TSV Integration without Front-side CMP Process

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Abstract
In this study, a low-cost through-multilayer TSV integration process has been developed. The features are that a double-layer spin coating technique is applied to prevent residual photoresist left inside TSVs. Besides, redistribution layer is
deposited before TSV filling in order to eliminate the front-side CMP process, which will lower the fabrication cost. Basic electrical tests of single layer chip are performed in order to pick out these known good dies for stacking. A given mass of stacking TSV integration samples are fabricated. Electrical test results are
presented to show the quality of TSV interconnects and TSV isolation. The quality of bonding strength is characterized through shear tests, and the optimized bonding parameters are put forward after a set of experiments with different parameter
combinations. The mean of bonding precision is 3.31μm, with the bonding yield being 94.17%. Thermodynamic simulation is simulated to characterize the stress and warping values of this multi-layers TSV integration. All test results support the good quality of this through-multilayer integration approach.

Index Terms—3D packaging, through silicon via, memory stacking, bonding strength

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Informasi Detail

Judul Seri

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No. Panggil

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Penerbit

: IEEE., 2016

Deskripsi Fisik

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Bahasa

English

ISBN/ISSN

0894-6507

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

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Subjek

SEMIKONDUKTOR

Info Detail Spesifik

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Pernyataan Tanggungjawab

ETY

Versi lain/terkait

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