Ditapis dengan
Analysis of Temperature Distribution in Stacked IC With On-Chip Sensing Devic…
Abstract Temperature distributions in 3-D integrated circuits (ICs) are analyzed with a test structure, which has a top-tier chip attached on a bottom dummy chip with adhesive layer. The devices with four kinds of top-tier chip thickness tSi of 50–410 μm were fabricated by a standard 0.18 μm CMOS process. The test structure consists of 24 sensor blocks, each of which has sensor p-n diodes…
- Edisi
- VOL. 28, NO. 3, AUGUST 2015
- ISBN/ISSN
- 0894-6507
- Deskripsi Fisik
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015
- Judul Seri
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015
- No. Panggil
- -
A Rigorous 3-D NAND Flash Cost Analysis
Abstract Scaling challenges with NAND flash have forced manufacturers to consider monolithic 3-D process and device architectures as potential successor technologies. Those that involve a vertical cylindrical channel are regarded as favorites. These include bit-cost scalable (BiCS) NAND, pipe-shaped bit-cost scalable (p-BiCS) NAND, and terabit cell array transistor (TCAT) NAND. It has been ass…
- Edisi
- VOL. 26, NO. 4, NOVEMBER 2013
- ISBN/ISSN
- 0894-6507
- Deskripsi Fisik
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 26, NO. 4, NOVEMBER 2013
- Judul Seri
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 26, NO. 4, NOVEMBER 2013
- No. Panggil
- -
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