Ditapis dengan
Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor
Abstract In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being match…
- Edisi
- VOL. 28, NO. 2, MAY 2015
- ISBN/ISSN
- 0894-6507
- Deskripsi Fisik
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 2, MAY 2015
- Judul Seri
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 2, MAY 2015
- No. Panggil
- -
A Regularized Singular Value Decomposition-Based Approach for Failure Pattern…
Abstract In semiconductor manufacturing processes, monitoring the quality of wafers is one of the most important steps to quickly detect process faults and significantly reduce yield loss. Fail bit maps (FBMs) represent the failed cell count during wafer functional tests and have been popularly used as one of the diagnosis tools in semiconductor manufacturing for process monitoring, root caus…
- Edisi
- VOL. 28, NO. 1, FEBRUARY 2015
- ISBN/ISSN
- 0894-6507
- Deskripsi Fisik
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 1, FEBRUARY 2015
- Judul Seri
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 1, FEBRUARY 2015
- No. Panggil
- -
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