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Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With …
Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-node upset. This paper presents a novel memory cell design as variant of the DICE cell (that is tolerant to only a single event with a single-node upset). The proposed design is referred to as TDICE and uses transistors to block the paths that connect a node to the next node in the feedback loop of the m…
- Edisi
- VOL. 14, NO. 1, MARCH 2014
- ISBN/ISSN
- DOI: 10.1109/TDMR.20
- Deskripsi Fisik
- IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014
- Judul Seri
- IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
- No. Panggil
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The Flip Side of Financial Synergies: Coinsurance Versus Risk Contamination
This paper characterizes when joint financing of two projects through debt increases expected default costs, contrary to conventional wisdom. Separate financing dominates joint financing when risk-contamination losses—that are associated with the contagious default of a well-performing project that is dragged down by the other project’s poor performance— outweigh standard coinsurance …
- Edisi
- -
- ISBN/ISSN
- -
- Deskripsi Fisik
- The Review of Financial Studies / v 26 n 12 2013
- Judul Seri
- The Review of Financial Studies
- No. Panggil
- -
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