e-journal

ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.18-um Salicided CMOS Technology

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Abstract
One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra “ESD implantation” mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18- m salicided CMOS process is investigated by experimental testchips. The second breakdown current ( 2) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.

Index Terms—CMOS, diode, electrostatic discharge (ESD) implantation, ESD protection, snapback breakdown.

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Informasi Detail

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 2, MAY 2005

No. Panggil

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Penerbit

: IEEE., 2005

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 2, MAY 2005

Bahasa

English

ISBN/ISSN

0894-6507

Klasifikasi

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Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

VOL. 18, NO. 2, MAY 2005

Subjek

SEMIKONDUKTOR
DIODA

Info Detail Spesifik

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Pernyataan Tanggungjawab

ETY

Versi lain/terkait

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