Scratching of Patterned Cu/Dielectric Surface Layers by Pad Asperities in CMP

Abstract—In chemical-mechanical polishing (CMP), as the rough polymer pad slides over patterned structures of metal interconnects and dielectrics the pad asperities themselves, though soft, may scratch the relatively hard layers. The fully plastically deformed pad asperities with high interfacial friction are the primary sources of pad scratching. In this paper, scratching of Cu/dielectric li…

Scheduling of Single-Arm Multi-cluster Tools With Wafer Residency Time Constr…

Abstract—This paper studies the challenging problem of scheduling single-arm multi-cluster tools with wafer residency time constraints. They have a linear topology and their bottleneck tool is process-bound. This work aims to find an optimal one-wafer cyclic schedule. With the Petri net model developed in our previous work and the minimal cycle time for a multicluster tool without wafer resi…

Scheduling In-Line Multiple Cluster Tools

Abstract—A cluster tool which is widely used for wafer fabrication processes consists of several processing modules (PMs), a transport robot, loadlocks, and an equipment front-end module (EFEM) in which a wafer cassette is loaded and unloaded. A wafer cassette with 25 identical wafers is transported by an overhead hoist transfer (OHT) between cluster tools and stored in a stocker when the co…

Scheduling and Analysis of Start-Up Transient Processes for Dual-Arm Cluster …

Abstract—The trends of increasing wafer diameter and smaller lot sizes have led to more transient periods in wafer fabrication. For some wafer fabrication processes, such as atomic layer deposition, wafers need to visit some process modules for a number of times, instead of once, thus leading to a so-called revisiting process. Most previous studies on cluster tool scheduling focus on steady s…

Regression Analysis of Low Kill Potential Defect Mechanisms (Moving Beyond Co…

Abstract—A means of measuring the yield influence for high density, low kill potential defect mechanisms is presented. The method can be applied to wafers individually and is only, marginally more expensive to implement than a least squares fit, but has a much smaller standard error and provides a clear indicator of impact on yield. The ability to tolerate up to 50% outliers enables the metho…

Randomized General Regression Network for Identification of Defect Patterns i…

Abstract—Defect detection and classification in semiconductor wafers has received an increasing attention from both industry and academia alike. Wafer defects are a serious problem that could cause massive losses to the companies’ yield. The defects occur as a result of a lengthy and complex fabrication process involving hundreds of stages, and they can create unique patterns. If these patt…

Production Planning and WIP Assignment for Wafer Fabrication Tools With Avail…

Abstract—This paper deals with a short-term production plan of a single toolset during a shift at a semiconductor fabrication plant. We propose a cost-based optimization model that seeks to minimize the cost of the shift while meeting the following conditions: 1) the shift produces its required output, measured in work-in-process (WIP) levels; 2) preventive maintenance (PM) tasks are carried …

Process Development and Optimization for 3 μm High Aspect Ratio Via-Middle T…

Abstract—This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 μm top entrant critical dimension and 50 μm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3…

Phase Transformation of Monocrystalline Silicon Induced by Polishing With Dia…

Abstract—A newly developed semi-fixed flexible polishing tool called sol-gel (SG) polishing pads can satisfy the polishing demand of silicon wafers with scratch-free and nanoroughness surface. However, an obvious damage layer emerges on the surface of monocrystalline silicon wafer after polished by SG polishing pads with diamond abrasives. In this paper, combined characterizations consist of …

Pattern-Independent PMD Layer Planarization by Controlling its Volume Before CMP

Abstract—We achieved excellent planarization for a pre-metal dielectric (PMD) layer regardless of its pattern density distribution by making the distribution uniform before chemical mechanical polishing (CMP) without any stopper layer. The distribution control was done by lithography using a checkered reticle on the high-density PMD area followed by etching of the PMD layer to uniformize the…

Particle Transport in Etching Chamber Influenced by Coulomb Force

Edisi

VOL. 28, NO. 3, AUGUST 2015

ISBN/ISSN

0894-6507

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

No. Panggil

-

Particle Reduction and Control in Plasma Etching Equipment

Abstract—Particles within plasma etching equipment stick to the wafer and cause defects, resulting in large scale integrated circuit (LSI) yield reduction.We observed the behavior of particles resuspended in a vacuum chamber using a laser light scattering method. Investigating the influences of gases, static electricity, and plasma on particle resuspension, we found out that particles are no…

Optimization of Re-Entrant Hybrid Flows With Multiple Queue Time Constraints …

Abstract—This paper proposes optimization methods of re-entrant hybrid flows with multiple queue time constraints in batch processes of semiconductor manufacturing. A smoothing flow concept and a dispatching rule for the re-entrant flows called “re-entrant flow smoothing” [REFS(X)] and a loading rule for the processes with multiple queue time constraints called “synchronized control of…

Observation and Elimination of Recoil Particles From Turbo Molecular Pumps

Abstract—The existence of recoil particles from the turbo molecular pump has been verified. The recoil particles may be the root cause of yield degradation for the vacuum processes such as the plasma etching processes. To eliminate the recoil particles, they must be trapped inside the turbo molecular pump or inside the manifold chamber. After experimenting with various materials and designs,…

Novel Approaches to Optimizing Carrier Logistics in Semiconductor Manufacturing

Abstract—This paper provides an overview of new approaches for assessing and addressing requirements for carrier logistics in semiconductor manufacturing and discusses solutions for optimizing the efficiency of capital equipment installed in the fab. An exploration of crucial influencing factors (both on the material handling as well as on the equipment side) will be followed by a discussion …

Non-Contact, Sub-Surface Detection of Alloy Segregation in Back-End of Line C…

Abstract—Alloy seedlayers for copper back-end of line interconnects have become common at technology groundrules of 45 nm and below, due to reliability requirements. The key requirement of the minority alloy component (e.g., Al or manganese, also referred to as the “dopant”) is that it segregates to the copper (Cu)/dielectric cap layer interface in order to promote adhesion between the C…

Multi-Strata Stealth Dicing Before Grinding for Singulation-Defects Eliminati…

Abstract—We report on defects characterization and reduction as well as die strength enhancement using stealth dicing (SD) on high-backside reflectance (82%) 2-D NAND memory wafers. This is performed using three-strata subsurface infrared (1.342 μm) nanosecond pulsed laser die singulation with a partial-SD before grinding integration approach. In this paper, a combination of simulation, cha…

Multiblock Principal Component Analysis Based on a Combined Index for Semicon…

Abstract—The purposes of multivariate statistical process control (MSPC) are to improve process operations by quickly detecting when process abnormalities have occurred and diagnosing the sources of the process abnormalities. In the area of semiconductor manufacturing, increased yield and improved product quality result from reducing the amount of wafers produced under suboptimal operating co…

Modeling, Analysis, Simulation, Scheduling, and Control of Semiconductor Manu…

Abstract—This paper presents a Petri net approach to modeling, analysis, simulation, scheduling, and control of semiconductor manufacturing systems. These systems can be characterized as discrete event systems that exhibit sequential, concurrent, and conflicting relations among the events and operations. Their evolution is dynamic over time. The system complexity is tremendous owing to the co…

Modeling and Optimal Design of a Glass RTP System

Abstract—The problem of modeling and generating an optimal design of a rapid thermal processing (RTP) system for flat panel display glass was addressed. An RTP system using bulb-type tungsten-halogen lamps was considered, and a dynamic model to describe the glass temperature distribution was established. The power dispersion function comprising the model was established in an experimental R…

Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor

Abstract In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being match…

Measuring the Manufacturing Yield for Skewed Wire Bonding Processes

Abstract In semiconductor manufacturing, the technologies of stacked semiconductor packaging are important miniaturization strategies in which excellent quality is essential for a good reputation. Yield-based index Cpk has been the most popular tool for successful quality improvement activities and quality program implementation in multichip package processes. For in-plant applications, quali…

Measurement and Analysis of Seismic Response in Semiconductor Manufacturing E…

Abstract In this paper, a cost-effective, easy-install and fast measurement and analysis method to obtain seismic response of semiconductor manufacturing equipments was developed and its validity was discussed. In the developed method, micro-vibration measurement experiments are first carried out to obtain transfer functions and coherence functions from the floor to arbitrary part of equipment…

Material Removal Mechanism in Chemical Mechanical Polishing: Theory and Modeling

Abstract The abrasion mechanism in solid-solid contact mode of the chemical mechanical polishing (CMP) process is investigated in detail. Based on assumptions of plastic contact over wafer-abrasive and pad-abrasive interfaces, the normal distribution of abrasive size and an assumed periodic roughness of pad surface, a novel model is developed for material removal in CMP. The basic model is = r…

Manufacturing Yield for Multiple Lines Gold Bumping Processes With Asymmetric…

Abstract Development of touch display driver IC (TDDI) has enabled slimmer smartphone design by virtue of the integration of touch controller and display driver ICs (DDIs) into a single chip. TDDI plays an important role in touch integrated display panels. Compared to conventional DDI, TDDI requires more bonding pads for touch applications, thus increasing the usage of gold. The requirement to…

Manufacturing Challenges of GaN-on-Si HEMTs in a 200mm CMOS Fab

Abstract In this paper, we report on the challenges related to growth and processing of 200mm GaN-on-Si wafers in a CMOS fab. We describe the Au free process we developed as well as how we assure wafer quality prior processing. For the first time, we analyze possible Ga contamination issues related to the processing of GaN wafers and we present the cleaning procedures we developed to avoid it…

Makespan Analysis of Lot Switching Period in Cluster Tools

Abstract Cluster tools each of which consists of processing modules (PMs), a transport robot and loadlocks perform most wafer fabrication processes in semiconductor manufacturing. Recently, the lot size has been decreasing from 25 wafers to even 7-8 wafers due to the larger wafer size and circuit width reduction especially in large scale integration (LSI) manufacturing. Hence, the lot switchin…

Lot Size Management in the Semiconductor Industry: Queueing Analysis for Cycl…

Abstract In semiconductor manufacturing, production units (wafers) are transferred and processed in lots. While the current convention is a lot size of 25 wafers in semiconductor manufacturing, there has been much discussion about changing this standard to a smaller value. The principal motivation behind moving to smaller lot sizes is to decrease the average cycle time of a wafer. In this pape…

Light Interference Map: A Prescriptive Optimization of Lithography-Friendly L…

Abstract Achieving lithography-friendly layout typically involves repeated heuristic optimization and lithography simulations, and so is very time-consuming. We propose a light interference map (LIM), in which the value of a particular location represents the extent of potential light interference to nearby patterns if some patterns are relocated (or some new patterns are introduced) to that…

In Search of “Forever,” Continued Transistor Scaling One New Material at …

Abstract This work looks at past, present, and future material changes for the metal–oxide–semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moore’s law, new materials and structures are required. The first major material change to extend Moo…

Improvement of Rough Interface Between Barrier/Seed Layer and Porous Ultralow…

Abstract With critical dimension of device scaled down to 28 nm technological node and beyond, porous ultralow k (PULK) film as an insulator is used in Cu interconnects to further reduce resistance–capacitance (RC) delay. The integration of the PULK film faces more severe challenges due to the presence of porosity. Plasma treatments and wet cleaning processes have been considered to be cri…

Improved Variable EWMA Controller for General ARIMA Processes

Abstract The exponentially weighted moving average (EWMA) controller is a popular run-to-run control scheme in semiconductor manufacturing because of its effectiveness and simplicity. In this paper, we propose an improved variable EWMA controller design method. The optimal discount factor of the EWMA controller is determined by minimizing the mean square error of process output at each run. Th…

Implementation of Tungsten Metallization In Multilevel Interconnection Techno…

Abstract The techniques of experimental design and response-surface methodology have been used to produce empirical models of the deposition and etchback of tungsten in commercially available reactors for a tungsten plug technology. Deposition was carried out in a Genus 8402 LPCVD batch reactor by the Hz reduction of WF,. Responsesurfaces for deposition rate, sheet resistance uniformity, resi…

Impact of Linewidth on Backend Dielectric TDDB and Incorporation of the Linew…

Abstract Low-k time-dependent dielectric breakdown (TDDB) has been found to vary as a function of metal linewidth, when the distance between the lines is constant. Modeling requires determining the relationship between TDDB and layout geometries. Therefore, comb test structures that vary pattern density and linewidth independently have been designed and implemented in 45 nm technology. Models …

Impact of Gate Induced Drain Leakage on Overall Leakage of Submicrometer CMOS…

Abstract In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal–oxide–semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in sca…

How Target Physical Properties Affect Thin-Body Semiconductor Doping When Usi…

Abstract In this paper, the authors investigate how target sputtering, dose retention, and damage formation is generated in thin-body semiconductors by means of energetic ion impacts. The problems associated with ion implanting or plasma doping Si thin-bodies are well documented, however, it is not clear how changing the target material to other semiconductors currently being considering for …

Health Index Extraction Methods for Batch Processes in Semiconductor Manufact…

Abstract This paper deals with a study of three methods for health index (HI) extraction in semiconductor manufacturing equipments. The first method uses degradation reconstruction-based identification with basic principal component analysis (PCA), the second one uses multiway PCA and the last one extracts HI from the significant points related to degradation. A comparison of these methods are…

Full-Wafer Voltage Contrast Inspection for Detection of BEOL Defects

Abstract This paper details an application where E-beam inspection (EBI) can be used for 100% full wafer inspection, generally considered a mythical target for EBI. For process layers where the line-widths and defects of interest are large, very large pixel size and high scan frequency can be used, thereby making full wafer inspection feasible. The metal layers in the back-endof-line fit this …

Fluorocarbon Chemistry: A 0-Dimensional Model for Oxide and Nitride Dry Etching

Abstract In this paper, a 0-dimensional model for the understanding of dry etching characteristics in silicon oxide and nitride materials is reported. The model is applied to analyze the etching performances in a design of experiments where gas mixtures are varied in the fluorocarbon chemistry typical of the “protected sidewall” regime. The modeling analysis of flat sample etching allows f…

Flexible Pressure Sensors Based on Screen-Printed P(VDF-TrFE) and P(VDF-TrFE)…

Abstract This paper presents large-area-printed flexible pressure sensors developed with an all screen-printing technique. The 4 × 4 sensing arrays are obtained by printing polyvinylidene fluoride-trifluoroethylene P(VDF-TrFE) and their nanocomposite with multi-walled carbon nanotubes (MWCNTs) and are sandwiched between printed metal electrodes in a parallel plate structure. The bottom electr…

Feedback Control System of Wafer Temperature for Advanced Plasma Processing a…

Abstract A wafer temperature feedback control system during plasma processing with rapid, precise, and real-time temperature monitoring employing frequency-domain low-coherence interferometry was developed. To keep the temperature within a specific range, plasma was actively switched on and off, controlled by signals from a monitoring system. It was applied to an organic film etching process w…

Fault Detection Using the k-Nearest Neighbor Rule for Semiconductor Manufactu…

Abstract It has been recognized that effective fault detection techniques can help semiconductor manufacturers reduce scrap, increase equipment uptime, and reduce the usage of test wafers. Traditional univariate statistical process control charts have long been used for fault detection. Recently, multivariate statistical fault detection methods such as principal component analysis (PCA)-based…

Fast Scheduling of Semiconductor Manufacturing Facilities Using Case-Based Re…

Edisi

VOL. 29, NO. 1, FEBRUARY 2016

ISBN/ISSN

0894-6507

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 29, NO. 1, FEBRUARY 2016

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 29, NO. 1, FEBRUARY 2016

No. Panggil

-

Fabrication, Characterization, and Simulation of a Low-cost TSV Integration w…

Abstract In this study, a low-cost through-multilayer TSV integration process has been developed. The features are that a double-layer spin coating technique is applied to prevent residual photoresist left inside TSVs. Besides, redistribution layer is deposited before TSV filling in order to eliminate the front-side CMP process, which will lower the fabrication cost. Basic electrical tests of…

ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.1…

Abstract One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra “ESD implantation” mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18- m salicided CMOS process is investigated by experimental testchips. The second breakdown current ( 2) o…

Equipment Effectiveness: OEE Revisited

Edisi

VOL. 18, NO. 1, FEBRUARY 2005

ISBN/ISSN

0894–6507

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 1, FEBRUARY 2005

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 1, FEBRUARY 2005

No. Panggil

-

Enhancement of the Virtual Metrology Performance for Plasma-Assisted Oxide Et…

Abstract Virtual metrology (VM) model based on plasma information (PI) parameter for C4F8 plasma-assisted oxide etching processes is developed to predict and monitor the process results such as an etching rate with improved performance. To apply fault detection and classification or advanced process control models on to the real-mass production lines efficiently, high-performance VM model is …

Effects of Polishing Parameters on Evolution of Different Wafer Patterns Duri…

Abstract Chemical mechanical polishing (CMP) has been widely used in the IC industry. To specify proper polishing parameters for Cu CMP is a very important and difficult task. In this paper, by using the linear system method modeling the relationship between the contact pressure and topography of wafer, the evolutions of the wafer patterns under different polishing parameters are simulated an…

Effects of Abrasive Size Distribution in Chemical Mechanical Planarization: M…

Abstract Recently, a comprehensive model has been developed by Luo and Dornfeld (“Material removal mechanism in chemical mechanical polishing: theory and modeling,” IEEE Trans. Semiconduct. Manufact., vol. 14, pp. 112–133, May 2001) to explain the material removal mechanism in chemical mechanical planarization (CMP). Based on the model, the abrasive size distribution influences the mate…

Effect of Plasma Process for SiO2 Film on Sidewall

Abstract We evaluated the physical and electrical characteristics of SiO2 treated by plasma oxidation on top and sidewall. The plasma process is less effective for SiO2 on sidewall than on top and further less for small pattern. Both the characteristics for SiO2 on sidewall are sensitive to plasma condition in deposition sequence, while not for SiO2 on top. When the plasma process is used as …