Yield Prediction Through the Event Sequence Analysis of the Die Attach Process

Abstract—Die attach is the process of mounting a plurality of dice to a printed circuit board (PCB) or substrate. Die attach is critical to the thermal and electrical performance of semiconductor products, significantly affecting the final yield of PCBs. In general, the die attacher records alarm events, change events, and maintenance events in a log. Alarm events occur when dice are not alig…

Wafer Surface Charging Model for Single-Wafer Wet-Spin Processes

Abstract—Wet chemical processes in integrated circuit (IC) manufacturing are used in many applications, e.g., post-etch residue removal and pre-deposition surface treatment. While advanced single-wafer wet spin tools are part of the critical toolset for advanced IC fabrication, non-optimized tool hardware and/or process may induce different types of wafer surface charging issues. In this pap…

Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale …

Abstract—Wafer maps can exhibit specific failure patterns that provide crucial details for assisting engineers in identifying the cause of wafer pattern failures. Conventional approaches of wafer map failure pattern recognition (WMFPR) and wafer map similarity ranking (WMSR) generally involve applying raw wafer map data (i.e., without performing feature extraction). However, because increasin…

Wafer Map Defect Detection and Recognition Using Joint Local and Nonlocal Lin…

Abstract—In semiconductor manufacturing processes, defect detection and recognition in wafer maps have received increasing attention from semiconductor industry. The various defect patterns in wafer maps provide crucial information for assisting engineers in recognizing the root causes of the fabrication problems and solving them eventually. This paper develops a manifold learning-based wafer…

Variability Improvement by Si Surface Flattening of Electrical Characteristic…

Abstract—Variability improvement of metal-oxidesemiconductor field-effect transistors (MOSFETs) characteristics with high-k HfON gate insulator by Si surface flattening was investigated. The Si surface flattening process was carried out by Ar/4.9%H2 anneal utilizing rapid thermal annealing system. The HfON gate insulator was formed by the in-situ Ar/O2 plasma oxidation of HfN utilizing elect…

Using Wafer Map Features to Better Predict Die-Level Failures in Final Test

Abstract—In semiconductor manufacturing, wafer fabrication is followed by chip assembly where individual dies are assembled as a packaged chip. In between, dies are tested in terms of their electrical properties and those which fail to pass the “wafer test” are filtered out. However, some faulty dies pass the test and cause a packaged chip to fail in the final test. The inaccuracy of the …

Uniformity Control of 3-D Stacked ICs: Optical Metrology and Statistical Anal…

Abstract—This paper evaluates various optical metrology techniques for in-line control of the niformity of 3-D stacked structures. Key process steps during 3-D integration flow were identified and characterized in order to quantify their specific intra-wafer dispersion signature. The cross correlation between the various intra-wafer process step signatures was then analyzed to verify the data…

Tutorial on Applying the VM Technology for TFT-LCD Manufacturing

Abstract—In the high-tech industries, on-line quality monitoring on each workpiece under processing is required to ensure process stability and improve yield rate. However, conducting workpiece-by-workpiece actual metrology is very expensive and time-consuming. In this case, a novel idea is to use “virtual metrology” (VM) that conjectures workpiece quality based on process data collected…

Tristate Inverter Array: A New Technology Development Yield Learning Vehicle …

Edisi

VOL. 28, NO. 4, NOVEMBER 2015

ISBN/ISSN

0894-6507

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015

No. Panggil

-

Through-Silicon-Via Fabrication Technologies, Passives Extraction, and Electr…

Abstract—Major advances have been made in the processing technologies of through-silicon-vias (TSVs) because TSV is an essential element for both wafer-level 3-D integration and packaging-based 3-D integration, due to its short interconnect length, high interconnect density, and small footprint. Based on a review of current TSV technologies, this paper reports a number of recently developed e…

Thermal Stress Effects on the Electrical Properties of p-Channel Polycrystall…

Abstract—We developed a method to compact the glass sheets of a flat-panel displays that use metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs), and the effects of thermal stress on the fabricated devices were compared against those of a bare-glass device. The glass substrate was exposed to a temperature of 650 ◦C for 40 h in order to …

Thermal Behavior of Residual Defects in Low-Dose Arsenic- and Boron-Implanted…

Abstract—We investigated the thermal behavior of defects remaining in low-dose (700 ◦C to remove residual damage as well as to activate impurities. Index Terms—Residual damage, ion implantation, rapid thermal annealing (RTA), silicon.

Temperature-Dependent Emissivity of Silicon-Related Materials and Structures

Abstract— The results of an ongoing collaborative project between the New Jersey Institute of Technology (NJIT) and SEMATECH on the temperature-dependent emissivity of siliconrelated materials and structures are presented in this study. These results have been acquired using a spectral emissometer. This emissometer consists of a Fourier Transform Infra-Red (FTIR) spectrometer designed specifi…

Study and Improvement on Tungsten Plug Corrosion in CMP Process for PCRAM

Abstract—To reduce the reset current for developing reliable high density phase change random access memory (PCRAM), small bottom electrode contact (BEC) size formation is a critical process. One of the failure mode for the process is the corrosion of tungsten plug, which is caused by tungsten chemical mechanical planarization (CMP) process. In this paper, this CMP process was analyzed. The t…

Step-Down Spatial Randomness Test for Detecting Abnormalities in DRAM Wafers …

Abstract—Defects on semiconductor wafers are not uniformly distributed, but tend to cluster. These spatial defect patterns contain useful information about issues during integrated circuit fabrication. Promptly detecting abnormal wafers is an important way to increase yield and product quality. However, research on identifying spatial defect patterns has focused only on flash memory with a s…

Statistical Comparison of Fault Detection Models for Semiconductor Manufactur…

Abstract—A variety of statistical and data-mining techniques have been developed for the fault detection (FD) modeling of semiconductor manufacturing processes over the past three decades. However, few studies have analyzed which models are adequate for different types of fault data. In this paper, we define a FD model as an algorithm combining feature extraction, feature selection, and class…

Stability and Control Performance Analysis of Double EWMA Controller With Met…

Abstract—This paper mainly focuses on establishing the stability conditions of the double exponentially weighted moving average (d-EWMA) controller with metrology delay when the process experiences a general disturbance and analyzing its control performance under some typical types of process disturbance. The necessary and sufficient conditions for stability are established by Routh–Hurwit…

Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

Abstract—Effective extraction of source/drain (S/D) series resistance is a challenging task owing to poor epi-growth and nonuniform distribution of current density in S/D, critical limitation of restrictive design rule, ultra thin contact film, and complicated 3-D fin-type field effect transistor (FinFET) structure. In this paper, we report a test structure for measurement of linear and nonli…

Semiconductor Manufacturing Process Monitoring Using Gaussian Mixture Model a…

Abstract—Fault detection has been recognized in the semiconductor industry as an effective component of advanced process control framework in increasing yield and product quality. Principal component analysis (PCA) has been applied widely to semiconductor manufacturing process monitoring. However, the unique characteristics of semiconductor processes—high dimension of data, nonlinearity in…

SiO2 Etching with Aqueous HF: Design and Development of a Laboratory-Scale In…

Abstract—Etching of SiO2 films using aqueous HF-based chemistries is widely used in integrated circuit and microelectromechanical device industries. To precisely control film loss during cleaning or etching processes, good control over the contact time between the wet chemistry and the substrate is necessary. An integrated wet etch and dry reactor system has been designed and fabricated by s…

Scratching of Patterned Cu/Dielectric Surface Layers by Pad Asperities in CMP

Abstract—In chemical-mechanical polishing (CMP), as the rough polymer pad slides over patterned structures of metal interconnects and dielectrics the pad asperities themselves, though soft, may scratch the relatively hard layers. The fully plastically deformed pad asperities with high interfacial friction are the primary sources of pad scratching. In this paper, scratching of Cu/dielectric li…

Scheduling of Single-Arm Multi-cluster Tools With Wafer Residency Time Constr…

Abstract—This paper studies the challenging problem of scheduling single-arm multi-cluster tools with wafer residency time constraints. They have a linear topology and their bottleneck tool is process-bound. This work aims to find an optimal one-wafer cyclic schedule. With the Petri net model developed in our previous work and the minimal cycle time for a multicluster tool without wafer resi…

Scheduling In-Line Multiple Cluster Tools

Abstract—A cluster tool which is widely used for wafer fabrication processes consists of several processing modules (PMs), a transport robot, loadlocks, and an equipment front-end module (EFEM) in which a wafer cassette is loaded and unloaded. A wafer cassette with 25 identical wafers is transported by an overhead hoist transfer (OHT) between cluster tools and stored in a stocker when the co…

Scheduling and Analysis of Start-Up Transient Processes for Dual-Arm Cluster …

Abstract—The trends of increasing wafer diameter and smaller lot sizes have led to more transient periods in wafer fabrication. For some wafer fabrication processes, such as atomic layer deposition, wafers need to visit some process modules for a number of times, instead of once, thus leading to a so-called revisiting process. Most previous studies on cluster tool scheduling focus on steady s…

Regression Analysis of Low Kill Potential Defect Mechanisms (Moving Beyond Co…

Abstract—A means of measuring the yield influence for high density, low kill potential defect mechanisms is presented. The method can be applied to wafers individually and is only, marginally more expensive to implement than a least squares fit, but has a much smaller standard error and provides a clear indicator of impact on yield. The ability to tolerate up to 50% outliers enables the metho…

Randomized General Regression Network for Identification of Defect Patterns i…

Abstract—Defect detection and classification in semiconductor wafers has received an increasing attention from both industry and academia alike. Wafer defects are a serious problem that could cause massive losses to the companies’ yield. The defects occur as a result of a lengthy and complex fabrication process involving hundreds of stages, and they can create unique patterns. If these patt…

Production Planning and WIP Assignment for Wafer Fabrication Tools With Avail…

Abstract—This paper deals with a short-term production plan of a single toolset during a shift at a semiconductor fabrication plant. We propose a cost-based optimization model that seeks to minimize the cost of the shift while meeting the following conditions: 1) the shift produces its required output, measured in work-in-process (WIP) levels; 2) preventive maintenance (PM) tasks are carried …

Process Development and Optimization for 3 μm High Aspect Ratio Via-Middle T…

Abstract—This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 μm top entrant critical dimension and 50 μm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3…

Phase Transformation of Monocrystalline Silicon Induced by Polishing With Dia…

Abstract—A newly developed semi-fixed flexible polishing tool called sol-gel (SG) polishing pads can satisfy the polishing demand of silicon wafers with scratch-free and nanoroughness surface. However, an obvious damage layer emerges on the surface of monocrystalline silicon wafer after polished by SG polishing pads with diamond abrasives. In this paper, combined characterizations consist of …

Pattern-Independent PMD Layer Planarization by Controlling its Volume Before CMP

Abstract—We achieved excellent planarization for a pre-metal dielectric (PMD) layer regardless of its pattern density distribution by making the distribution uniform before chemical mechanical polishing (CMP) without any stopper layer. The distribution control was done by lithography using a checkered reticle on the high-density PMD area followed by etching of the PMD layer to uniformize the…

Particle Transport in Etching Chamber Influenced by Coulomb Force

Edisi

VOL. 28, NO. 3, AUGUST 2015

ISBN/ISSN

0894-6507

Deskripsi Fisik

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

Judul Seri

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

No. Panggil

-

Particle Reduction and Control in Plasma Etching Equipment

Abstract—Particles within plasma etching equipment stick to the wafer and cause defects, resulting in large scale integrated circuit (LSI) yield reduction.We observed the behavior of particles resuspended in a vacuum chamber using a laser light scattering method. Investigating the influences of gases, static electricity, and plasma on particle resuspension, we found out that particles are no…

Optimization of Re-Entrant Hybrid Flows With Multiple Queue Time Constraints …

Abstract—This paper proposes optimization methods of re-entrant hybrid flows with multiple queue time constraints in batch processes of semiconductor manufacturing. A smoothing flow concept and a dispatching rule for the re-entrant flows called “re-entrant flow smoothing” [REFS(X)] and a loading rule for the processes with multiple queue time constraints called “synchronized control of…

Observation and Elimination of Recoil Particles From Turbo Molecular Pumps

Abstract—The existence of recoil particles from the turbo molecular pump has been verified. The recoil particles may be the root cause of yield degradation for the vacuum processes such as the plasma etching processes. To eliminate the recoil particles, they must be trapped inside the turbo molecular pump or inside the manifold chamber. After experimenting with various materials and designs,…

Novel Approaches to Optimizing Carrier Logistics in Semiconductor Manufacturing

Abstract—This paper provides an overview of new approaches for assessing and addressing requirements for carrier logistics in semiconductor manufacturing and discusses solutions for optimizing the efficiency of capital equipment installed in the fab. An exploration of crucial influencing factors (both on the material handling as well as on the equipment side) will be followed by a discussion …

Non-Contact, Sub-Surface Detection of Alloy Segregation in Back-End of Line C…

Abstract—Alloy seedlayers for copper back-end of line interconnects have become common at technology groundrules of 45 nm and below, due to reliability requirements. The key requirement of the minority alloy component (e.g., Al or manganese, also referred to as the “dopant”) is that it segregates to the copper (Cu)/dielectric cap layer interface in order to promote adhesion between the C…

Multi-Strata Stealth Dicing Before Grinding for Singulation-Defects Eliminati…

Abstract—We report on defects characterization and reduction as well as die strength enhancement using stealth dicing (SD) on high-backside reflectance (82%) 2-D NAND memory wafers. This is performed using three-strata subsurface infrared (1.342 μm) nanosecond pulsed laser die singulation with a partial-SD before grinding integration approach. In this paper, a combination of simulation, cha…

Multiblock Principal Component Analysis Based on a Combined Index for Semicon…

Abstract—The purposes of multivariate statistical process control (MSPC) are to improve process operations by quickly detecting when process abnormalities have occurred and diagnosing the sources of the process abnormalities. In the area of semiconductor manufacturing, increased yield and improved product quality result from reducing the amount of wafers produced under suboptimal operating co…

Modeling, Analysis, Simulation, Scheduling, and Control of Semiconductor Manu…

Abstract—This paper presents a Petri net approach to modeling, analysis, simulation, scheduling, and control of semiconductor manufacturing systems. These systems can be characterized as discrete event systems that exhibit sequential, concurrent, and conflicting relations among the events and operations. Their evolution is dynamic over time. The system complexity is tremendous owing to the co…

Modeling and Optimal Design of a Glass RTP System

Abstract—The problem of modeling and generating an optimal design of a rapid thermal processing (RTP) system for flat panel display glass was addressed. An RTP system using bulb-type tungsten-halogen lamps was considered, and a dynamic model to describe the glass temperature distribution was established. The power dispersion function comprising the model was established in an experimental R…

Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor

Abstract In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being match…

Measuring the Manufacturing Yield for Skewed Wire Bonding Processes

Abstract In semiconductor manufacturing, the technologies of stacked semiconductor packaging are important miniaturization strategies in which excellent quality is essential for a good reputation. Yield-based index Cpk has been the most popular tool for successful quality improvement activities and quality program implementation in multichip package processes. For in-plant applications, quali…

Measurement and Analysis of Seismic Response in Semiconductor Manufacturing E…

Abstract In this paper, a cost-effective, easy-install and fast measurement and analysis method to obtain seismic response of semiconductor manufacturing equipments was developed and its validity was discussed. In the developed method, micro-vibration measurement experiments are first carried out to obtain transfer functions and coherence functions from the floor to arbitrary part of equipment…

Material Removal Mechanism in Chemical Mechanical Polishing: Theory and Modeling

Abstract The abrasion mechanism in solid-solid contact mode of the chemical mechanical polishing (CMP) process is investigated in detail. Based on assumptions of plastic contact over wafer-abrasive and pad-abrasive interfaces, the normal distribution of abrasive size and an assumed periodic roughness of pad surface, a novel model is developed for material removal in CMP. The basic model is = r…

Manufacturing Yield for Multiple Lines Gold Bumping Processes With Asymmetric…

Abstract Development of touch display driver IC (TDDI) has enabled slimmer smartphone design by virtue of the integration of touch controller and display driver ICs (DDIs) into a single chip. TDDI plays an important role in touch integrated display panels. Compared to conventional DDI, TDDI requires more bonding pads for touch applications, thus increasing the usage of gold. The requirement to…

Manufacturing Challenges of GaN-on-Si HEMTs in a 200mm CMOS Fab

Abstract In this paper, we report on the challenges related to growth and processing of 200mm GaN-on-Si wafers in a CMOS fab. We describe the Au free process we developed as well as how we assure wafer quality prior processing. For the first time, we analyze possible Ga contamination issues related to the processing of GaN wafers and we present the cleaning procedures we developed to avoid it…

Makespan Analysis of Lot Switching Period in Cluster Tools

Abstract Cluster tools each of which consists of processing modules (PMs), a transport robot and loadlocks perform most wafer fabrication processes in semiconductor manufacturing. Recently, the lot size has been decreasing from 25 wafers to even 7-8 wafers due to the larger wafer size and circuit width reduction especially in large scale integration (LSI) manufacturing. Hence, the lot switchin…

Lot Size Management in the Semiconductor Industry: Queueing Analysis for Cycl…

Abstract In semiconductor manufacturing, production units (wafers) are transferred and processed in lots. While the current convention is a lot size of 25 wafers in semiconductor manufacturing, there has been much discussion about changing this standard to a smaller value. The principal motivation behind moving to smaller lot sizes is to decrease the average cycle time of a wafer. In this pape…

Light Interference Map: A Prescriptive Optimization of Lithography-Friendly L…

Abstract Achieving lithography-friendly layout typically involves repeated heuristic optimization and lithography simulations, and so is very time-consuming. We propose a light interference map (LIM), in which the value of a particular location represents the extent of potential light interference to nearby patterns if some patterns are relocated (or some new patterns are introduced) to that…

In Search of “Forever,” Continued Transistor Scaling One New Material at …

Abstract This work looks at past, present, and future material changes for the metal–oxide–semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moore’s law, new materials and structures are required. The first major material change to extend Moo…